Daily Update – Day 15
– Cleaned the new workplace in the laboratory.
– Organized the the new workplace in the laboratory. In particular the computer was moved on the desk in order to attach the DE1-SoC board to the computer.
– Read an overview of the DE1-SoC board on Altera website. Link for the overview : http://www.altera.com/education/univ/materials/boards/de1-soc/unv-de1-soc-board.html
– Watched a demonstration video of the DE1-SoC board. Link for the video demo : http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836&PartNo=5
– Read the DE1-SoC board hardware specifications. Link for the specifications : http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836&PartNo=2
Link for the board layout : http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836&PartNo=3
– Read all documents that came together with the DE1-SoC board, including the Quick Start Guide, which was the most important one.
– Ran a power test on the DE1-SoC board. Also ran a VGA output test on the board.
– Downloaded DE1-Soc System CD, user manual and a file named “Learning Roadmap”. These documents will be explored tomorrow.
Saturday :
– Started reading the User Manual of the DE1-SoC board.
– Read the Learning Roadmap file contained in the DE1-SoC User Manual. The learning roadmap file shows a standard learning path in how to use the DE1-SoC board.
Note : The documentation about the DE1-SoC board seems more complete and clearer than the documentation about the DE2 board that we started working with.
– Read the Getting Started Guide contained in the DE1- SoC User Manual. Skimmed through the section “Running LXDE on the DE1-SoC board” and skipped the section “Running Linux on the DE1-SoC board”. The LXDE is short for Lighweight X11 Desktop Environment, which is a desktop environment that uses a minimal amount of resources ( such as energy, CPU and RAM ). In order to boot a Linux OS or run the LXDE in the DE1-SoC board, a microSD ( SD stands for Secure Digital ) card with a capacity of at least 8 GB is required. These are very interesting features, and may be explored next week.
– Downloaded and installed the software : SoC Embedded Design Suite from Altera. This software is used to design and develop software for the hard core ARM Cortex A9 processor. An important note is that many drivers were installed to manage communication between the computer and external ARM based processors.
Link for the SoC EDS download : http://dl.altera.com/soceds/?edition=subscription
Read MoreDaily Update – Day 14
– No significant work was done. This day was used to work on another project, a low level designed thermometer.
Read MoreDaily Update – Day 13
– Received a DE1-SoC Development and Education board from Altera. The board contains a Cyclone® V FPGA, model [ 5CSEMA5F31C6N ], and this FPGA has a hard core processor ARM Cortex A9®. One of the next steps should be researching about the hard core processor ARM Cortex A9® and compare it to the soft core processor Nios® II that we have been using.
– Installed the Quarthus® II Web Edition version 14.0 on another computer in the laboratory. The computer that we were working with had shown some problems with the CAD tools, which is the reason to install the tools in another computer, a seemingly less used one. Also we needed the Quarthus® II Web Edition version 14.0 to work with the Cyclone V FPGA in the new DE1-SoC board.
Read MoreDaily Update – Day 12
– Finally run a “Hello World” message on a simple Nios II soft core processor !!!!!!!!!
Hello World
It worked on my personal computer, which leads us to believe that the OS or some other external factor is the cause of the error in the laboratory computer.
– Asked Professor Gene to reformat or clean the computer in the laboratory, which seems to have 2 viruses:
- The Display driver is halting and recovering constantly.
- The search engine [ Google ] is being redirected to a bing page with lots of advertisement.
– Started reading about the command line for curiosity, got scared and ran away.
– Answered a survey from Altera regarding FPGAs. Link to the survey : http://www.surveygizmo.com/s3/1698288/SoC-FPGAs-What-Do-You-Think
Read MoreDaily Update – Day 11
– Found out that the SOPC builder present in most tutorials about SOPC design is being substituted by the Qsys.
– Installed the Quarthus® II Web Edition version 13.sp1 on my personal computer again. It seems to be working, more tests will be done tomorrow.
– Still struggling to make an application for a designed Nios® II soft core processor. When downloading the application to the FPGA, the error [ Failure to download .elf file ] shows up. Went to Altera® forum and read about this error. Possible causes of the error:
- The connections made during the Nios II design are wrong in some way that makes the processor not work properly. For example, the clock and reset cables may be linked and the processor is always reseting itself. Checked for this possibility and it doesn’t seem to be the case.
- The IP usage license expired. After a week the IP license expires and to window pops up whenever a design is downloaded into the FPGA. If this window is exited, then the design downloaded into the FPGA stops working. This is a measure to stop people from designing and shipping their design without an IP usage license. During the download, trials were made with the window untouched, but that does not seem to be the problem.
- The Eclipe IDE for software development to Nios® II may contain bugs. A true bug was already found in the process of project creation, but in this case a way around was available. This is a possible explanation for the error. A possible way around is using the command line, but that would take some time. A note is that Altera is working in its SOPC design tools, and both versions 13.1 and 14 of the Quarthus® software have updates in the Eclipse IDE and the Qsys®. Trying the new software could be a solution for this error, but a cyclone 4 FPGA would be needed to use Quarthus® II version 14.
- The OS or another external factor may be causing the error. In Altera forum was a report of a person who looked everywhere for the cause of this bug and couldn’t solve it, but after reinstalling the OS and the Quarthus® II Web Edition the error was gone.
– Went through the following tutorials :
- “How to Run a Nios II Application Using Quarthus II and Qsys”. Went through the entire tutorial for the third time. My understanding about the tools grew with each trial on this tutorial, specially because i tried to modify it slightly and observe what happened on the development environment. Although, had no success in running an application for the designed Nios® II soft core processor. Link for this tutorial : https://www.youtube.com/watch?v=kS7pAp5EWRQ
- “Qsys + Nios II simple test”. This tutorial also uses Qsys® to design a simple Nios® II. The interesting part is that the tutorial fails to run an application for the designed Nios® II with the same error happening on the laboratory. Link for this tutorial : https://www.youtube.com/watch?v=HQdE3XKWykk
- Several other tutorials, talks and classes about the Qsys® and the Eclipe IDE for software development to a customized Nios® II soft core processor.
Note: Some of the work above was done in the weekend.
Read More
Daily Update – Day 10
– Experimented in the Eclipse IDE for software development to a Nios® II soft core processor. Some of the experiments were:
- File creation. Which files are created upon project creation and compilation, when they are created, what is the purpose of each file.
- Interface navigation.
- Effects of settings on the IDE interface and in the software development.
– Watched online tutorials for software development in the Eclipse IDE:
- “Hello World on your FPGA”. This tutorial shows how to print a “hello world” message on the LCD screen of the FPGA through programming in VHDL for a simple Nios® II soft core processor designed with the SOPC builder. Link for this tutorial : https://www.youtube.com/watch?v=gBknFw511s0&list=LL48speL6HPyLooIqQOEFQ4Q&index=3
- “My First Nios II tutorial part 1”. This tutorial shows how to design a simple Nios® II soft core processor with the SOPC builder software and download it into an FPGA. The tutorial is helpful because the SOPC builder software and the Qsys software installed in the laboratory computer are similar . Link for this tutorial : https://www.youtube.com/watch?v=DBkza5-SlqQ
- “My first Nios II part 2”. This tutorial shows how to develop code for a simple Nios® II soft core processor and download the code in the FPGA configured with the simple Nios® II. The template code for the “hello word” message is altered to blink some LEDs on the FPGA and then downloaded into the on-chip memory of the Nios® II soft core processor within the FPGA.
