Daily Update – Day 9
– Read the software development tutorial for a Nios® II soft core processor in chapter 9 of the book “Embedded SoPC Design With Nios® II Processor And VHDL Examples”. The tutorial uses the SOPC builder to create a Nios® II design and the Eclipse based Integrated Development Interface (IDE) to develop software for the designed Nios® II. The laboratory computer has the Qsys software installed and not the SOPC builder. Although the Qsys and the SOPC builder accomplish the same function, which is the design of System On A Chip (SOC) or a System on A Programmable Chip (SOPC), their interfaces are different.
– Watched the software design part of the tutorial “How to Run Nios II Application Using Quarthus and Qsys”. In this tutorial a simple “hello world” message is printed in the console of the Eclipse IDE for software development to a Nios® II soft core processor. Went through the tutorial, but the “hello world” message did not appear on the console for some unknown reason. Link for the tutorial : https://www.youtube.com/watch?v=kS7pAp5EWRQ
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Daily Update – Day 8
– Finished the chapter 9 tutorial of the book “Embedded SoPC Design With Nios® II Processor And VHDL Examples”. The tutorial implements a Nios® II soft core processor through the Qsys® software, which is included in the Quarthus® Web Edition software from Altera. The Nios® II soft core processor can be customized before downloading it’s design into an FPGA. Two files are particularly important after the compilation of the Nios® II customized design : .sopcinfo and .sopc. The first contains information vital to create programs for the Nios® II (such as the processor custom features), and the latter contains the information required to configure an FPGA with the customized Nios® II design.
– Run tests on the Qsys® and Quarthus® softwares to understand better the development cycle. In particular when each file type is created. Also researched on the purpose of each file type.
– Started researching how to program the implemented Nios® II soft core processor. The language used to program the processor is C, and the IDE used is an Eclipse IDE specific for the Nios® II processor. Before programming for the Nios® II processor, it is required information regarding the specific Nios® II design, and this information is contained in the .sopcinfo file generated after the compilation of the Nios® II.
Read MoreDaily Update – Day 7
– Continued to struggle with the chapter 9 of the book “Embedded SoPC Design With Nios® II Processor And VHDL Examples” tutorial to create and configure a Nios® II processor.
– Found a helpful online video tutorial on Nios® II creation and software development that helped with some steps of tutorial in the book. This video tutorial shows how to create a Nios® II using the Qsys software, which is the one installed in the laboratory computer. Link for the video tutorial : https://www.youtube.com/watch?v=kS7pAp5EWRQ
Read MoreDaily Update – Day 6
– Read chapter 8 of the book “Embedded SoPC Design With Nios® II Processor And VHDL Examples”. The chapter gives an overview of the Nios® II processor features. The Nios® II processor is intelectual property ( IP ) of Altera. Usually the Nios® II is implemented in VHDL codes to be programmed into a configurable logic circuit device, such as an FPGA, and therefore it is a soft core processor in contrast to a transistor level hard core processor.
– Started the tutorial in chapter 9 of the book “Embedded SoPC Design With Nios® II Processor And VHDL Examples”. Had some problems due to differences in the interfaces of the software installed in the laboratory computer and the tutorial in the book. The book shows the SoPC builder tool, and the software in the laboratory has the QSys. The SoPC builder tool and QSys are similar, but their interfaces are different.
Read MoreDaily Update – Day 5
– Finished the 15 minutes tutorial in the beginning of the book “Rapid Prototyping of Digital Systems – SOPC edition” in the laboratory computer. No difficulty presented itself to simulate the compiled FPGA configuration, but to configure the FPGA with the compiled configuration first the installation of the driver “USB-Blaster” from Altera was needed. This driver controls the communication between the Quarthus® II software and the FPGAs from Altera, allowing the configuration of the FPGA with the compiled setup made in the Quarthus® II software through a USB cable. The driver file was downloaded together with the Quarthus® II Web Edition software, but required manual installation on the computer. Information about the driver installation procedure can be found at : http://www.altera.com/download/drivers/usb-blaster/dri-usb-blaster-vista.html
Note : The FPGA used in the project is a Cyclone II EP2C35F672C6 with EPCS16 16-Mbit serial configuration device.
– Talked with the project supervisor about some questions regarding the project. Some of the questions were:
- What are the advantages of FPGAs over CPLDs and PALs ?
- Why does FPGAs have buffer circuits before the inputs and after the outputs ?
- Compilation steps in the Quarthus® II software: Analysis / Sysnthesis, Fitter (place and route), Assembler, Timing Analysis and Netlist Writter.
- Project schedule, next steps.
– Started reading the Nios® II tutorial in the book “Rapid Prototyping of Digital Systems – SOPC edition”. This tutorial goes from pages 322 to 347.
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Daily Update – Day 4
– Downloaded and installed the following software on my personal notebook:
- Quarthus® II Web Edition, version 13.0sp1. The Quarthus® II Web Edition is composed by the Quarthus® II (which includes Nios® II processor Embedded Development Suite) and ModelSim-Altera Edition (which includes the Starter Edition).
- Device support for Cyclone® II, Cyclone® III and Cyclone® IV FPGA groups.
- Quartus® II Help.
The download took approximately 4 hours. The software above was found at the Altera download center. Link for download center : http://dl.altera.com/13.0sp1/?edition=web
– Started implementing the 15 minutes tutorial at the beginning of the book “Rapid Prototyping of Digital Systems – SOPC edition” on my personal notebook. The tutorial goes from page 1 to page 41 of the latter book. The FPGA configuration in the tutorial was successfully compiled, but some difficulties appeared to simulate and to download the compiled FPGA configuration into the Altera DE2® development board. Possible causes of these difficulties : Downloaded software files were corrupted; the installation wasn’t completely successful; the software installed does not work properly on the Operational System (OS) Windows® 8.
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